VLSI implementation of a multi-mode turbo/LDPC decoder architecture

Flexible and reconfigurable architectures have gained wide popularity in the communications field. In particular, reconfigurable architectures for the physical layer are an attractive solution not only to switch among different coding modes but also to achieve interoperability. This work concentrates on the design of a reconfigurable architecture for both turbo and LDPC codes decoding. The novel contributions of this paper are: i) tackling the reconfiguration issue introducing a formal and systematic treatment that, to the best of our knowledge, was not previously addressed; ii) proposing a reconfigurable NoCbased turbo/LDPC decoder architecture and showing that wide flexibility can be achieved with a small complexity overhead. Obtained results show that dynamic switching between most of considered communication standards is possible without pausing the decoding activity. Moreover, post-layout results show that tailoring the proposed architecture to the WiMAX standard leads to an area occupation of 2.75 mm2 and a power consumption of 101.5 mW in the worst case

Area Efficient DST Architectures for HEVC

This work analyses the actual throughput of the Discrete Sine Transform (DST) stage in a realistic HEVC encoder, which executes the rate-distortion optimization algorithm to achieve high compression quality. Then, a low complexity DST factorization, where all the integer multiplications are substituted with add-and-shift operations, is exploited to design an efficient 1D-DST core. The proposed 1D-DST core is employed to derive two area efficient architectures, namely Folded and Full-parallel, for computing the 4×4 2D-DST in HEVC. Finally, the proposed 2D-DST architectures are synthesized on a 90-nm standard cell technology to support the actual target throughput required to encode 4K UHD @30fps video sequences, showing better area efficiency with respect to existing DST architectures for HEVC

On optimal and near-optimal turbo decoding using generalized max operator

Motivated by a recently published robust geometric programming approximation, a generalized approach for approximating efficiently the max* operator is presented. Using this approach, the max* operator is approximated by means of a generic and yet very simple max operator, instead of using additional correction term as previous approximation methods require. Following that, several turbo decoding algorithms are obtained with optimal and near-optimal bit error rate (BER) performance depending on a single parameter, namely the number of piecewise linear (PWL) approximation terms. It turns out that the known max-log-MAP algorithm can be viewed as special case of this new generalized approach. Furthermore, the decoding complexity of the most popular previously published methods is estimated, for the first time, in a unified way by hardware synthesis results, showing the practical implementation advantages of the proposed approximations against these method